Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 351)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 351
6 SPI Busy Bit:
0: Ready for next read or write access
1: Busy. The SPI clock is still toggling. 0 SPP: r
7 Enable GPP Boot SPI Flash Program Interface
0: Program Interface disabled. Bit 0 is always 1. Write to GPP Boot
SPI Flash Data Register is ignored and read deliver 0.
Only GPP has access to the GPP Boot SPI flashes
1: Program Interface enabled. Chip Select is controlled by Bit 0 and
read and write accesses to GPP Boot SPI Flash Data Register are
accepted.
SPP has access to the GPP Boot SPI flashes.
Note: The write value is synchronized with falling edge of GPP
platform reset PLTRST_.
When this bit is set 1 to enable the Program interface this register
must be polled and only when this bit is read 1 the SPP has the
ownership of the interface. When the bit is 1 the SPP can access one
the GPP SPI flashes.
When this bit is set 0 this register must be polled until the bit is read
0. When the bit is low the GPP is owner of GPP Boot SPI Flash
interface. 0 SPP: r/w
Table 8-169 GPP Boot SPI Flash Data Register
Address: 0xD3
Bit Description Default Access
7:0 GPP Boot SPI Flash Write Data Register.
A write triggers 8 SPI clocks and shifts the data out to MOSI. The
Data on MISO is shifted in. - SPP: w
GPP Boot SPI Flash Data Register.
Contains the data shifted in by the last write access to GPP Boot SPI
Flash Data Register 0 SPP: r
Table 8-168 GPP Boot SPI Flash Control Register (continued)
Address: 0xD2
Bit Description Default Access