Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 256)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 256
Table 8-20 DMC Base FPGA force golden image or reload image Register
Address: 0x11
Bit Description Default Access
7:0 Writing a magic byte to register triggers following action:
0x3C: Reload DMC Base FPGA configuration with
DMC_FPGA_PROG_ low pulse.
0xA5: Force Golden image with DMC_FORCE_GOLDEN high pulse 0 w
Table 8-21 DMC 1 FPGA force golden image or reload image Register
Address: 0x12
Bit Description Default Access
7:0 Writing a magic byte to register triggers following action:
0x3C: Reload DMC 1 FPGA configuration with DMC1_FPGA_PROG_
low pulse.
0xA5: Force Golden image with DMC1_FORCE_GOLDEN high pulse 0 w
Table 8-22 DMC 2 FPGA force golden image or reload image Register
Address: 0x13
Bit Description Default Access
7:0 Writing a magic byte to register triggers following action:
0x3C: Reload DMC 2 FPGA configuration with DMC2_FPGA_PROG_
low pulse.
0xA5: Force Golden image with DMC2_FORCE_GOLDEN high pulse 0 w