3 reset structure, Table 8-23, Table 8-24 – Artesyn ATCA-8310 Installation and Use (May 2014) User Manual
Page 257: Table 8-25, Cpld and fpga
CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E)
257
8.1.3
Reset Structure
There is one asynchronous reset domain CPLD_PWR_GOOD.
Table 8-23 RTM FPGA device 0 force golden image or reload image Register
Address: 0x14
Bit Description
Default
Access
7:0
Writing a magic byte to register triggers following action:
0x3C: Reload RTM FPGA configurations with RTM_FPGA_PROG_
low pulse.
0xA5: Force Golden image with RTM0_FORCE_GOLDEN high pulse
0
w
Table 8-24 RTM FPGA device 1 force golden image or reload image Register
Address: 0x15
Bit Description
Default
Access
7:0
Writing a magic byte to register triggers following action:
0x3C: Reload RTM FPGA configurations with RTM_FPGA_PROG_
low pulse.
0xA5: Force Golden image with RTM1_FORCE_GOLDEN high pulse
0
w
Table 8-25 RTM FPGA device 2 force golden image or reload image Register
Address: 0x16
Bit Description
Default
Access
7:0
Writing a magic byte to register triggers following action:
0x3C: Reload RTM FPGA configurations with RTM_FPGA_PROG_
low pulse.
0xA5: Force Golden image with RTM2_FORCE_GOLDEN high pulse
0
w