Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 258)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 258
The power-up reset signal CPLD_PWR_GOOD resets all internal registers and state machines to
their default values.
8.1.4 Clocking Scheme
There are three clock domains inside the CPLD. The 1st clock domain is sourced by the internal
22 MHz clock and comprises the following logic blocks:
 Power Up State Machine
 Glue Logic
 Register Logic
The 2nd clock domain is sourced by the IPMC SPI Master Interface and compromises the
following block:
 IPMC SPI Slave
The 3rd clock domain is sourced by the Glue Logic FPGA SPI Master Interface and compromises
the following block:
 FPGA SPI Slave
The entire logic blocks are running with the same clock at the same frequency. All signals from
other clock domains are synchronized to the corresponding clock domain.
8.1.5 Logic Blocks
8.1.5.1 IPMC Watchdog
The IPMC Watchdog implemented in the CPLD emulates the external watchdog device
MAX6373KA.
The timeout is controllable by the IPMC signal H8S_WDOG_SET. When the level is low (the
default after power-up or IPMC reset) the timeout is 10s otherwise the timeout is 1s.
The Watchdog goes active after 3 H8S_WDI level changes and H8S_WDOG_ACTIVE is driven
high. The watchdog is now armed.
When the Watchdog is active the watchdog needs to be service before the watchdog bites
after the timeout. Watchdog is serviced with each level change of H8S_WDI.