Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 425)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 425
Soft = Soft Reset
Allows updating the serial configuration prom of the FPGA
8.4.2.10.1 Configuration Prom Update Control Register
Address: 0xD8, CfgPrmUpdCtrReg
Width: 8 bit
Controls the update of the FPGA serial configuration prom by the host processor via SPI bus.
Table 8-221 Configuration Prom Update Control Register
Bit Acronym Type Description Default Pwr Soft
7 CodePrgIfEn RW Enable Code Program Interface
0b1: CodePrgIfEn, Program
Interface enabled. Chip Select is
controlled by Bit 0 of this register
and read and write accesses to
Code SPI Data Register initiate
serial transmission
0b0: CodePrgIfDis, Program
Interface disabled. Bit 0 of this
register is ignored. Write and
read to Code SPI Data Register
are ignored. 0b0 X X
6 ConfigSpiBusy R Read type of read command for
SPI-flash
0b1: ConfigSpiBusy, Wait for
ready until next access to
CfgPrmUpdDatReg
0b0: ConfigSpiReady,
CfgPrmUpdDatReg can be
accessed - - -
5...2 - - reserved undef - -