Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 330)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 330
5 DMC Base Fault
0: No event
1: DMC Base Fault occurred. Ext. SPP: r/w1c
6 DMC 1 Fault
0: No event
1: DMC 1 Fault occurred. Ext. SPP: r/w1c
7 DMC 2 Fault
0: No event
1: DMC 2 Fault occurred. Ext. SPP: r/w1c
8 RTM Fault
0: No event
1: RTM Fault occurred. Ext. SPP: r/w1c
9 SPP Reset:
0: No event
1: SPP reset occurred or power-up cycle
Note: Bit is not maskable 1 SPP: r/w1c
15:10 Reserved 0 r
Table 8-134 Fault Event Enable Register
Address Offset: 0x84 - 0x85
Bit Description Default Access
0 SPP Watchdog expired enable:
0: Event disabled
1: Event enabled 0 SPP: r/w
1 Software Fault 1 enable:
0: Event disabled
1: Event enabled. 0 SPP: r/w
Table 8-133 Fault Event Status Register (continued)
Address Offset: 0x82 - 0x83
Bit Description Default Access