Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 279)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 279
2 Received Data is available. In FIFO mode, trigger level was reached; in non-FIFO
mode, RBR has data.
2 Receiver Time out occurred. It happens in FIFO mode only, when there is data in the
receive FIFO but no activity for a time period.
3 Transmitter requests data. In FIFO mode, the transmit FIFO is half or more than half
empty; in non-FIFO mode, THR is read already
4 Modem Status: one or more of the modem input signals has changed state
Table 8-54 Interrupt Identification Register (IIIR)
IO Address: Base + 2
Bit
Description
Default Access
0 Interrupt status bit:
1: no interrupt pending
0: interrupt pending 1 GPP: r
2:1 Interrupt priority level and source:
11: Receiver line status
10: Receiver data available
01: Transmitter holding register empty
00: Modem status 0 GPP: r
3 Time Out Detected:
0: No time out interrupt is pending
1: Character time-out indication (FIFO mode only) 0 GPP: r
5:4 Reserved 0 r
7:6 FIFO Mode Enable bits:
00: Default mode
01: Reserved
10: Reserved
11: FIFO mode 0 GPP: r
Table 8-53 UART Interrupt Priorities2 (continued)
Priority Level Interrupt Source