Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 432)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 432
Pwr = Power On Reset
Soft = Soft Reset
The phy can be accessed via MDIO bus through this register with a simple bit bang interface.
8.4.2.13.1 MDIO Bit Bang Register
Address: 0xFC, MdioBitBang
Width: 8 bit
Allows to control and to read the status of an MDIO bus to the rPhy.
Table 8-228 MDIO Bit Bang Register
Bit Acronym Type Description Default Pwr Soft
7 - - reserved undef - -
6 MdioRead R 0b1: MdioReadHigh, if Mdio line
(Data) of I2c is high
0b0: MdioReadLow, if Mdio line
(Data) of I2c is low undef F F
5 MdioDirSet RW 0b1: MdioAsOutputSet, Mdio line
(Data) of I2c is driven by Dsp Fpga
0b0: MdioAsInputSet, Mdio line
(Data) of I2c is not driven by Dsp Fpga,
thus data from Phy can be read 0b0 X X
4 MdioValIfOutSet RW 0b1: MdioValSetHigh, Mdioline
(Data) of I2c is driven high by Dsp
Fpga if direction is set as output
0b0: MdioValSetLow, Mdio line (Data)
of I2c is driven low by Dsp Fpga if
direction is set as output 0b0 X X
3 - - reserved undef - -
2 MdcRead R 0b1: MdcReadHigh, if Mdc line
(Clock) of Mdio bus is high
0b0: MdcReadLow, if Mdc line (Clock)
of Mdio bus is low undef F F