Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 84)

Functional Description
ATCA-8310 Installation and Use (6806800M72E) 84
The peripheral set includes: three Telecom Serial Interface Port (TSIPs), an 16/8 bit Universal
Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA
Slave] port; two 10/100/1000 Ethernet media access controllers (EMACs), which provide an
efficient interface between the TCI6486 DSP core processor and the network a management
data input/output (MDIO) module (shared by both EMACs) that continuously polls all 32 MDIO
addresses in order to enumerate all PHY devices in the system, a Serial RapidIO with two 1x
lanes and support for packet forwarding; a 32-bit DDR2 SDRAM interface; 12 64-bit general-
purpose timers; an inter-integrated circuit bus module (I2C), 16 general-purpose input/output
ports (GPIO) with programmable interrupt/event generation modes and a 16-bit multiplexed
host-port interface (HPI16).
4.4.1.1 DSP Configuration
Following interfaces are not used and disable by strapping option:
 UTOPIA Interface
 TSIP Interface 1 and 2
 EMAC Interface 1
The DSPs run with 500 MHz core clock.
4.4.1.2 Boot Mode Selection
The desired boot mode is selected by setting the four boot mode select pins
BOOTMODE<3..0>, which are sampled during reset. The BOOTMODE can be set simultaneous
for all DSP via DSP-FPGA register.
Following boot modes are supported:
 Slave I2C boot (BOOTMODE = 4)
 EMAC Port 0 (BOOTMODE =9) default
 SRIO Boot (BOOTMODE =11)
4.4.1.3 EMAC Boot Mode
The bootloader configures the EMAC peripheral if it is enabled in bit 5 of Options in the EMAC
boot parameter table, opens a transmit and receive channel, configures Rx Communications
Port Programming Interface (CPPI), and also routes EMAC Rx interrupt to 4, and Tx interrupt to
5. Then the bootloader transmits an Ethernet-ready frame out if it is enabled in bit 4 of Options.