Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 372)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 372
Features:
 Transmit and receive Telecom Serial Interface Port (TSIP) bridge to SERDES for up to 10
DSPs each with 2 links at a bandwidth of 32.768 Mbit/s. The DspFpga internal design is
further prepared to connect 12 DSPs of next generation with 4 links each but the pins will
not be provided with the current FPGA version.
 CRC32 secured data transmission across the SERDES interface between DSP- and RTM-
FPGA
 Frame aligned to the 8 kHz frame synchronization signal data transmission between DSP
module and RTM FPGA
 Pattern transmission (feed-in and reception) across the SERDES interface between Base-
Board and RTM via a supplemental channel
 Two pairs of pseudo random pattern generators and comparators with pattern
transmission in a selectable payload channel to TSIP interface and SERDES
 SPI slave interface
 SERDES control and status registers (SCI Interface) accessible via SPI interface
 Host event and module failure outputs
 DSP and Ethernet PHY Reset and NMI control via SPI interface
 DSP reset and boot status of 10 DSPs accessible via SPI interface. Additional pins for next
generation DSPs will be necessary but are not provided with the current FPGA version.
 Power control for the DSP module
 Base Board and module slot identifier
 32.768 MHz clock generation for 10 DSPs with the current FPGA version.
 8 kHz frame synchronization generation for 10 DSPs with the current FPGA version.
 Full synchronous design with two clock domains (32.768 MHz and 125 MHz)
8.4 DSP FPGA HW/SW interfaces
8.4.1 DSP FPGA Address map Overview