Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 358)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 358
If CONF_CRC_ERR is driven high there is only one way to reset it, reconfigure the FPGA.
8.2.3.10 Glue Logic FPGA Dual Configuration
A standard SPI flash device is used to store Golden and Working bitstream.
The Lattice devices don't support to force the device to load the Golden image. When the
Working image is valid the Working image will be loaded. With FPGA logic a feature is added
to force the device to load the Golden Image.
A rising edge of the Signal FORCE_GOLDEN triggers a state machine implemented with FPGA
standard logic. The state machine sends SPI Flash commands to the FPGA Code SPI flash, which
corrupts the Working Image by erasing the first 4KB of the Working Image.
SED checking does not impact the performance or operation of the user logic. The SED
check is done periodically every ~600ms.
When the Glue Code SPI Flash program interface is enabled (Bit 7 of Table "Glue Logic FPGA
Code SPI Control Register" on page 324 is set) SED checking is disabled. Otherwise the
configuration clock signal CCLK is driven by the internal configuration clock caused by a
device bug.
This state machine needs to be implemented for all bitstream versions.
This state machine is needed for all FPGA devices in the project.