Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 415)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 415
8.4.2.8 DMC Power Supply Control Block (DmcPwrCtrlBlk)
Resets:
Pwr = Power On Reset
Soft = Soft Reset
This Block performs the power sequencing for the DSP power supply. It contains a monitor
register to indicate the voltage which has caused a potential power supply failure after the DMC
has powered up. If one of the power supplies fails the DMC is powered down by the DspFpga
and the board is informed by the deactivating the DMC_PWRGD signal.
8.4.2.8.1 DMC Power Supply Monitor Register
Address:
0xB0, DmcPwrMonReg
Width: 8 bit
This register monitors power supply failures (power loss and power interrupt) to identify the
power supply which has caused a power down of the DMC.
1 DspHevIntrptMask1 RW 0b1: DspHevIntrptEnable1,
enables DspHev1 interrupt
generation 0b0 X X
0 DspHevIntrptMask0 RW 0b1: DspHevIntrptEnable0,
enables DspHev0 interrupt
generation 0b0 X X
Table 8-207 DSP Host Event Interrupt Status Mask Register (continued)
Bit Acronym Type Description Default Pwr Soft
Table 8-208 DMC Power Supply Monitor Register
Bit Acronym Type Description Default Pwr Soft
7...5 - - reserved undef - -