Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 435)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 435
SERDES link. To identify a packet Start_of_Packet (K27.7 character) and End_of_Packet (K29.7
character) are used. This corresponds to a total packet size of 245824 bits. Since the
transmission duration of the 245760 bits on the TSIP side is 125 μs and on the SERDES side the
transmission of one packet takes 122,912μs regarding the 10B/8B encoding/decoding schema
there are still 2,088μs or 4176 bit remaining for idle time.
In the first realization step, an interface to 10 TI tomahawk DSPs each with two TSIP links
TSIP_TX (0..1)(0..9) and TSIP_TR (0..1)(0..9) will be implemented.
8.4.3.3 Setting up SERDES links
When the Reset control block releases the SERDES block reset line, a Serdes specific reset
sequence is processed which is indicated below:
 Releasing PCS quad reset
 Waiting for TX PLL to lock
 Waiting for RX PLL to lock
 Releasing channel specific resets for TX and RX direction
If the TX PLL or RX PLL remain in an unlock state (status can be read in SerDesTrmStatReg and
SerDesRcvStatReg), the serdes specific reset sequence will not finish. Setting
CompResReg:SrdsQuadReset first high, then low will retrigger the sequence.
Before data transmission can be started, a link state procedure forces the transmit and receive
state machines to a synchronous state. Therefore, the transmit state machine sends 100
consecutive COMMA characters followed by minimal 16 IDLE pattern and then starting
payload data transmission. The receive state machine itself expects 80 consecutive COMMA
characters, then entering idle state waiting for valid start of frame delimiters. Since transmit
Figure 8-14 122,912μs SERDES frame
Start of
packet
Suppl.
Info.
CRC
End of
packet
Speech information
8 bits 16 bits 32 bits 8 bits 245760 bits 4176 bits
125 μs frame of Speech information