Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 324)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 324
8.2.2.3.27 Force CRC Error Register
8.2.2.3.28 Glue Logic FPGA Code SPI Update Registers
1 Mask SPI Configuration Flash SPRL Bit:
0: Flash protection scheme is frozen. SPRL bit is set after bit 7 of
Table 98 Glue Logic FPGA Code SPI Control Register is set.
1: Flash protection scheme can be changed. SPRL bit is not set after
bit 7 of Table 98 Glue Logic FPGA Code SPI Control Register is set. 0 SPP: r/w
7:2 Reserved 0 r
Table 8-121 Test Control and Status Register (continued)
Address: 0x70
Bit Description Default Access
Table 8-122 Force CRC Error Register
Address: 0x71
Bit Description Default Access
7:0 Force CRC Error.
0x3C: Force configuration CRC Error. CONF_CRC_ERR will be
driven high.
All other values: The Force CRC Error is disabled. Only real CRC
errors will drive CONF_CRC_ERR high. 0 SPP: r/w
IPMC: r/w
Table 8-123 Glue Logic FPGA Code SPI Control Register
Address: 0x72
Bit Description Default Access
0 FPGA Code SPI Chip Select Control
1: Drive SPI Chip Select high
0: Drive SPI Chip Select low. 1 SPP: r/w