Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 398)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 398
8.4.2.5.2 Serdes Receiver Status Register
Address: 0x81, SerDesRcvStatReg
Width: 8 bit
The Serdes receiver status is shown
8.4.2.5.3 Supplemental Test Pattern Receive Data Register
Address: 0x82, SupplTstPatDataRcvDatReg
Table 8-190 Serdes Receiver Status Register
Bit Acronym Type Description Default Pwr Soft
7 SerdesRcvPllLolFlag R 0b1: SerdesRcvPllLolFlag,
Set when the Serdes
receiver PLL has lost lock.
Reset by respective bit in
SerDesTrmCtrlReg 0b0 F F
6 SerdesRcvLosFlag R 0b1: SerdesRcvLosFlag,
set when the loss of signal 0b0 F F
5 SerdesRcvHasFoundCommaFlag R 0b1:
SerdesRcvHasFoundCom
maFlag, set when first
comma found, after
period with no commas. 0b0 F F
4 - - reserved undef - -
3 SerdesRcvPllLol R 0b1: SerdesRcvPllLol,
Shows actual status of
Serdes receiver PLL lock. 0b0 F F
2 SerdesRcvLos R 0b1: SerdesRcvLos,
current the loss of signal
status 0b0 F F
1 SerdesRcvHasFoundComma R 0b1:
SerdesRcvHasFoundCom
ma, current status of
comma detection 0b0 F F
0 - - reserved undef - -