Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 403)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 403
8.4.2.6.1 DSP and Phy Reset and Dsp NMI Control Register
Address: 0x98, DspPhyResNmiCtrlReg
Width: 32 bit
This register is used to control the reset pins of the 10 TI Tomahawk DSPs (TMS320TCI6486)
and the RGMII Phy device. For the DSPs, the boot mode can be selected
Table 8-198 DSP and Phy Reset and Dsp NMI Control Register
Bit Acronym Type Description Default Pwr Soft
31 PhyRes RW 0b1: PhyRes, activates the reset pin for
the RGMII Phy device. 0b1 X X
30...24 - - reserved undef - -
23 DspPorRes RW 0b1: DspPorRes, activates the Power-On-
Reset pin (POR_N) common to all DSPs
(Cold Reset) 0b1 X X
22...21 - - reserved undef - -
20...17 BootMode RW Specifies the boot mode of the DSPs
during Power On Reset or System Reset
0b0101: BootMode5, Slave I2C boot
0b1001: BootMode9, Ethernet MAC Port
0
0b1011: BootMode11, RIO1
0brrrr: reserved 0b1001 X X
16...10 - - reserved undef - -
9 DspReset9 RW 0b1: DspReset9, activates the Warm
Reset pin (DSP9_RST_N) for DSP9 0b0 X X
8 DspReset8 RW 0b1: DspReset8, activates the Warm
Reset pin (DSP8_RST_N) for DSP8 0b0 X X
7 DspReset7 RW 0b1: DspReset7, activates the Warm
Reset pin (DSP7_RST_N) for DSP7 0b0 X X
6 DspReset6 RW 0b1: DspReset6, activates the Warm
Reset pin (DSP6_RST_N) for DSP6 0b0 X X
5 DspReset5 RW 0b1: DspReset5, activates the Warm
Reset pin (DSP5_RST_N) for DSP5 0b0 X X