Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 348)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 348
8.2.2.3.39 DMC 2 SPI Access Registers
A write access to the DMC 2 SPI Control Register start the corresponding SPI access.
Table 8-162 DMC 1 SPI MS Word Data Register
Address: 0xC4 -0xC5
Bit Description Default Access
15:0 DMC 1 SPI MS Word Write Data Register.
Contains the write bits 31:16 for a DMC register write access - SPP: w
DMC 1 SPI MS Word Read Data Register.
Contains the data bits 31:16 of the selected DMC 32 bit register
when the DMC SPI access has terminated successfully.
Note: Read DMC 1 SPI MS Word Data Register content as long SPI
access not started. 0 SPP: r
Table 8-163 DMC 2 SPI Control Register
Address: 0xC8 - 0xC9
Bit Description Default Access
1:0 Reserved 0 r
7:2 DMC 2 address. Selects a 32 bit DMC register. 0 SPP: r/w
11:8 DMC 2 Byte Select. When the corresponding select bit is set the
corresponding byte of the selected DMC register can be accessed. 0 SPP: r/w
12 DMC 2 Command.
0: DMC read access
1: DMC write access 0 SPP: r/w
13 Reserved 0 r
14 DMC 2 Access Abort. Flag
0: DMC SPI Slave access normal termination
1: DMC SPI Slave didn't response 0 SPP: r
15 DMC SPI Busy Bit:
0: Ready for next read or write access
1: Busy. The DMC SPI interface is still active. 0 SPP: r