Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 282)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 282
In the Line Control Register (LCR), the system programmer specifies the format of the
asynchronous data communications exchange. The serial data format consists of a start bit
(logic 0), five to eight data bits, an optional parity bit, and one or two stop bits (logic 1). The
LCR has bits for accessing the Divisor Latch and causing a break condition. The programmer
can also read the contents of the Line Control Register. The read capability simplifies system
programming and eliminates the need for separate storage in system memory.
Table 8-57 Line Control Register (LCR)
IO Address: Base + 3
Bit
Description
Default Access
1:0 Serial character WORD length:
00: 5 bits
01: 6 bits
10: 7 bits
11: 8 bits 0 GPP: r/w
2 Stop bit length:
1: 1.5 stop bits for 5 bit WORD length
1: 2 stop bits for 6, 7, and 8 bit WORD length
0: 1 stop bit for any serial character WORD length 0 GPP: r/w
3 Parity enable/disable
When bit 3 is set, a parity bit is generated in transmitted data
between the last data WORD bit and the first stop bit. In received
data, if bit 3 is set, parity is checked. When bit 3 is cleared, no parity
is generated or checked.:
1: Parity enabled
0: Parity disabled 0 GPP: r/w
4 Parity even/odd
When parity is enabled and bit 4 is set, even parity (an even
number of logic ones in the data and parity bits) is selected. When
parity is disabled and bit 4 is cleared, odd parity (an odd number of
logic ones) is selected.:
1: Even parity
0: Odd parity 0 GPP: r/w