Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 422)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 422
8.4.2.9.8 Component Reset Register
Address: 0xC7, CompResReg
Width: 8 bit
The bits of this register reset the respective components, e.g. Sedes Quad. Writing a 1 to a bit
puts the respective component into reset, until writing a 0 reenables its function again.
8.4.2.9.9 Dsp Fpga Version Register
Address: 0xC8, FpgaVersionReg
Width: 32 bit
3...0 ModuleFunctionalId R codes functional version
of Dsp Fpga environment
0b0001: DspNum2,
number of connected
Dsps is 2
0b0010: DspNum5,
number of connected
Dsps is 5
0b0011: DspNum10,
number of connected
Dsps is 10
0brrrr: reserved const - -
Table 8-215 Module Functional Identifier (continued)
Bit Acronym Type Description Default Pwr Soft
Table 8-216 Component Reset Register
Bit Acronym Type Description Default Pwr Soft
7...1 - - reserved undef - -
0 SrdsQdReset RW 0b1: SrdsQdReset, Serdes Quad is reset 0b0 X X