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Table 8-227, I2c bit bang register, Cpld and fpga – Artesyn ATCA-8310 Installation and Use (May 2014) User Manual

Page 430

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CPLD and FPGA

ATCA-8310 Installation and Use (6806800M72E)

430

Soft = Soft Reset

The Dsps 0...9 can be accessed via I2c bus through this registers with a simple bit bang
interface.

8.4.2.12.1 I2C Bit Bang Register

Addresses:

0xF0, I2CBitBang0

0xF1, I2CBitBang1

0xF2, I2CBitBang2

0xF3, I2CBitBang3

0xF4, I2CBitBang4

0xF5, I2CBitBang5

0xF6, I2CBitBang6

0xF7, I2CBitBang7

0xF8, I2CBitBang8

0xF9, I2CBitBang9

Width: 8 bit

Allows to control and to read the status of an I2C bus to the respective DSP.

I2CBitBang0 Register is connected to Dsp0, I2CBitBang1 Register is connected to Dsp1 and so
on.

Table 8-227 I2C Bit Bang Register

Bit

Acronym

Type

Description

Default

Pwr

Soft

7

-

-

reserved

undef

-

-

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