Table 8-31, Post code register, Cpld and fpga – Artesyn ATCA-8310 Installation and Use (May 2014) User Manual
Page 267
CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E)
267
8.2.2.1.3 POST Code Register
The FPGA provides an 8 bit wide register to store POST codes to the LPC I/O address 0x80. The
two nibbles of the register are converted to 7 segment codes and are displayed as two hex
values by two 7 segment LED Displays.
Table 8-31 POST Code Register
LPC I/O Address: 0x80
Bit
Description
Default
Access
7:0
POST codes from host
0
GPP: r/w
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