Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 413)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 413
The bits of this register mask the bits of the DspWdgStaReg for the generation of the Host
Event Interrupt (HOUT).
Table 8-206 DSP Watchdog Interrupt Status Mask Register
Bit Acronym Type Description Default Pwr Soft
15...10 - - reserved undef - -
9 DspWdgIntrptMask9 RW 0b1: DspWdgIntrptEnable9,
enables DspWdg9 interrupt
generation 0b0 X X
8 DspWdgIntrptMask8 RW 0b1: DspWdgIntrptEnable8,
enables DspWdg8 interrupt
generation 0b0 X X
7 DspWdgIntrptMask7 RW 0b1: DspWdgIntrptEnable7,
enables DspWdg7 interrupt
generation 0b0 X X
6 DspWdgIntrptMask6 RW 0b1: DspWdgIntrptEnable6,
enables DspWdg6 interrupt
generation 0b0 X X
5 DspWdgIntrptMask5 RW 0b1: DspWdgIntrptEnable5,
enables DspWdg5 interrupt
generation 0b0 X X
4 DspWdgIntrptMask4 RW 0b1: DspWdgIntrptEnable4,
enables DspWdg4 interrupt
generation 0b0 X X
3 DspWdgIntrptMask3 RW 0b1: DspWdgIntrptEnable3,
enables DspWdg3 interrupt
generation 0b0 X X
2 DspWdgIntrptMask2 RW 0b1: DspWdgIntrptEnable2,
enables DspWdg2 interrupt
generation 0b0 X X
1 DspWdgIntrptMask1 RW 0b1: DspWdgIntrptEnable1,
enables DspWdg1 interrupt
generation 0b0 X X
0 DspWdgIntrptMask0 RW 0b1: DspWdgIntrptEnable0,
enables DspWdg0 interrupt
generation 0b0 X X