Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 397)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 397
8.4.2.5.1 Serdes Receiver Control Register
Address: 0x80, SerDesRcvCtrlReg
Width: 8 bit
A Serdes reset or resync can be initiated via this register
Table 8-189 Serdes Receiver Control Register
Bit Acronym Type Description Default Pwr Soft
7 SerdesRcvPllLolFlagReset RW 0b1:
SerdesRcvPllLolFlagReset,
resets the loss of lock flag
bit in SerDesRcvStatReg 0b0 X X
6 SerdesRcvLosFlagReset RW 0b1:
SerdesRcvLosFlagReset,
resets the loss of signal flag
bit in SerDesRcvStatReg 0b0 X X
5 SerdesRcvHasFoundCom
maFlagReset RW 0b1:
SerdesRcvHasFoundComm
aFlagReset, resets the not
found comma flag bit in
SerDesRcvStatReg 0b0 X X
4...2 - - reserved undef - -
1 SerdesRcvResync RW 0b1: SerdesRcvResync,
Serdes receiver starts
waiting for comma
characters again, a 1 to 0
transition starts waiting,
SerdesRcvHasFoundComm
a and
SerdesRcvHasFoundComm
aFlag bits in the serdes
receiver status register
show the progress. 0b0 X X
0 SerdesRcvReset RW 0b1: SerdesRcvReset, puts
the Serdes receiver into
reset, resync sequence is
sent automatically when
deactivated 0b0 X X