Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 255)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 255
8.1.2.2.6 Test Register
8.1.2.2.7 FPGA Control Registers
These registers can be used to trigger reload the configuration of each FPGA writing the magic
byte 0x3C.
These registers can be used to corrupt the working image of the configuration SPI flash of each
FPGA writing the magic byte 0xA5.
7:3 Reserved 0 SPI: r
Table 8-17 Power-up Failure Codes Part 6 Register (continued)
CPLD Address: 0x0D
Bit Description Default Access
Table 8-18 Test Register
CPLD Address: 0x0E
Bit Description Default Access
0 Emulate GPP THERMTRIP.
0: normal operation
1: Emulate GPP THERMTRIP assertion
Note: Clear before payload is enabled again. 0 SPI: r/w
7:1 Reserved 0 SPI: r
Table 8-19 Glue FPGA Force Golden Image or Reload Image Register
Address: 0x10
Bit Description Default Access
7:0 Writing a magic byte to register triggers following action:
0x3C: Reload Glue FPGA configuration with FPGA_PROG_
low pulse.
0xA5: Force Golden image with FORCE_GOLDEN high
pulse 0 SPI: w