Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 342)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 342
 Miscellaneous Interrupt Registers
Table 8-151 SPP Miscellaneous Interrupt Status Register
Address: 0xA8 - 0xA9
Bit Interrupt Signal Description Default Access
0 BASE_ETH_INT_ Base Ethernet Switch. Ext. SPP: r
1 SOL_BOOT_RDY_ Interrupt from TS (SOL Controller).
Each time the signal
SOL_BOOT_RDY_ toggles the
status bit is set. Write one to clear. Ext. SPP: r/w1c
2 GPP_PROCHOT_ GPP Processor Hot Ext. SPP: r
3 GPP_CATERR_ GPP Catastrophic Error Ext. SPP: r
4 SRIO_INT_ Interrupt Signal from SRIO Switch Ext. SPP: r
5 SPP_DIMM0_THERM_EV
ENT_ SPP DIMM thermal event 0 Ext. SPP: r
6 SPP_DIMM1_THERM_EV
ENT_ SPP DIMM thermal event 1 Ext. SPP: r
7 SPP_USB2_OC_ USB Over Current event Ext. SPP: r
8 SPP_RTC_IRQ_ RTC Interrupt forward to SPP Ext. SPP: r
15:9 - Reserved 0 r
Table 8-152 SPP Miscellaneous Interrupt Enable Register
Address: 0xAA - 0xAB
Bit Interrupt Signal Description Default Access
0 BASE_ETH_INT_ Base Ethernet Switch. enable:
0: Disabled
1:Enabled 0 SPP: r/w
1 SOL_BOOT_RDY_ Interrupt from TS (SOL Controller) enable:
0: Disabled
1:Enabled 0 SPP: r/w