Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 190)

U-Boot
ATCA-8310 Installation and Use (6806800M72E) 190
6.2.1.11 Memory Initialization
6.2.1.11.1 Persistent Memory
The Freescale P4080 provides a mechanism to configure the DDR3 devices into self-refresh
mode before an actual reset is performed. This feature is initiated by the glue logic FPGA, but
also requires configuring a P4080 external interrupt pin (interrupt 5) as "panic interrupt".
U-boot configures everything as required, but if the operating system re-configures the
interrupt controller it might disable the mechanism. To re-enable it, the following register
writes are necessary:
 Set register at address 0xfe0500a0 (EIVPR5 register) to 0x004f0000
 Set register at address 0xfe0500b8 (EILR5 register) to 0x000000f0
U-boot will not re-write the memory contents when it comes out of a reset (except power-up
reset). Instead, it will re-read the whole memory and check for ECC errors. Only for the case
that an ECC error is detected the memory is rewritten.
Refer to a description of the u-boot variables "pram", "pmem_disable" and "clear_mem_top" for
further options related to persistent memory.
6.2.1.11.2 Memory Interleaving
By default, U-boot disables memory interleaving. Depending on the application, it might be
desired to enable specific interleaving options for maximum performance.
The U-boot variable "hwconf" can be set to enable interleaving. Note that only two chip selects
(cs0 and cs1) are used on the ATCA-8310.
 Disable memory controller interleaving:
setenv hwconfig "fsl_ddr:ctlr_intlv=null"
or
setenv hwconfig
 Cacheline interleaving:
setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline"
 Page interleaving:
setenv hwconfig "fsl_ddr:ctlr_intlv=page"
 Bank interleaving