Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 417)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 417
Brings by SoftReset affected registers to power up state
8.4.2.9.2 Synchronization and Error Monitor Register
Address: 0xC1, SyncErrMonReg
Width: 8 bit
This register monitors the synchronization and error status of different functions. If a function
signals an out of sync or an error, the respective bit is set. It can be reset by writing the
respective bit in SyncErrMonResRegF
Table 8-209 Soft Reset Register
Bit Acronym Type Description Default Pwr Soft
31...8 Soft_RstMgckNmb W Magic number to allow write
execution
0xE99E94: Soft_RstMgckNmb,
Magic number, soft reset is only
provoked if this bits are written
simultaneously with this value - - -
7...1 - - reserved undef - -
0 SoftResPrvk W Provoke soft reset
0b1: SoftResPrvk, Provoke soft
reset - - -
Table 8-210 Synchronization and Error Monitor Register
Bit Acronym Type Description Default Pwr Soft
7...5 - - reserved undef - -
4 SciIntrpt R 0b1: SciIntrpt, The serdes client
interfaces reports an interrupt 0b0 F F
3 SerdesRcvError R 0b1: SerdesRcvError, The serdes
receiver reports errors 0b0 F F
2 SerdesTrmError R 0b1: SerdesTrmError, The serdes
transmitter reports errors 0b0 F F