Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 388)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 388
This registers controls test pattern transmission
Table 8-178 Test Pattern Generator Control Register
Bit Acronym Type Description Default Pwr Soft
7...6 - - reserved undef - -
5 TstPatGenContErrPrvk RW 0b1: TstPatGenContErrPrvk,
errors are inserted
continuously 0b0 X X
4 TstPatGenSingleErrPrv
k RW 0b1: TstPatGenSingleErrPrvk,
one error is inserted when the
bit changes from 0 to 1 0b0 X X
3 TstPatGenBitstInvert RW 0b1: TstPatGenBitstrInvert,
selects that test pattern
bitstream is sent inverted
0b0:
TstPatGenBitstrNotInvert,
selects that test pattern
bitstream is sent not inverted 0b0 X X
2 TstPatGenDestSel RW Specifies the pattern
destination:
0b1: TstPat2Dsp, selects that
test pattern are sent to Dsp
instead of data from Des2Tsip
block
0b0: TstPat2Ser, selects that
test pattern are sent into
Tsip2Ser block instead of data
from Dsp 0b0 X X
1 TstPatGenPatSel RW Specifies the pattern source:
0b1: TstPatGenPatPrbs,
selects the PRBS pattern
0b0: TstPatGenPatStatic,
selects the static pattern 0b0 XX X
0 TstPatGenTxPatEn RW 0b1: TstPatGenTxPatEn,
enables the pattern insertion 0b0 X X