Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 101)

Functional Description
ATCA-8310 Installation and Use (6806800M72E) 101
4.9.1.2 SPP-Reset
4.9.1.2.1 Cold Reset
A cold reset is issued by either the PORESET# or the HRESET# signal.
4.9.1.2.2 Warm Reset
Warm Reset is Is done by the software.
4.9.1.3 Reset Sources
4.9.1.3.1 Power-up Reset
The power-up reset (BRD_PWROK) is activated during power-up or power-down and is
deactivated when all onboard supply voltages are within their threshold voltages. Power-up
reset generates a Cold reset on ATCA-8310 resetting all attached onboard devices. The power-
up reset signal BRD_PWROK is connected to the Glue Logic FPGA which propagates it to the
PWROK input of the P4080 (respecting the PWROK input min. assertion of 99msec). The DDR3
DIMMs are reset directly from the processors individually per memory channel and CPU during
power-up only, according DDR specification.
4.9.1.3.2 Software Controlled Reset
Software is able to generate a Cold and a Warm reset. Depending on the configuration.
4.9.1.3.3 Face Plate Reset
A pinhole reset switch is available on the face plate. Hitting the face plate reset generates a
reset on ATCA-8310 resetting all attached onboard devices. The reset switch must be enabled
through IPMC.
The reset switch will be recessed and can be covered by overlay foil.
4.9.1.3.4 RTM Reset
An RTM reset causes a reset on ATCA-8310 resetting all attached onboard devices.