Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 345)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 345
8.2.2.3.37 DMC Base SPI Access Registers
A write access to the DMC Base SPI Control Register start the corresponding SPI access.
Table 8-156 KCS Status/Control Register
Address: 0xB2 -0xB3
Bit Description Default Access
7:0 KCS Status/Control Register.
Forwarded via SPP LPC to IPMC using LPC IO address 0xCA3 PWR_GOOD:0 SPP: r/w
15:8 Reserved 0 r
Table 8-157 DMC Base SPI Control Register
Address: 0xB8 - 0xB9
Bit Description Default Access
1:0 Reserved 0 r
7:2 DMC Base address. Selects a 32 bit DMC register. 0 SPP: r/w
11:8 DMC Base Byte Select. When the corresponding select bit is set the
corresponding byte of the selected DMC register can be accessed. 0 SPP: r/w
12 DMC Base Command.
0: DMC read access
1: DMC write access 0 SPP: r/w
13 Reserved 0 r
14 DMC Base Access Abort. Flag
0: DMC SPI Slave access normal termination
1: DMC SPI Slave didn't response 0 SPP: r
15 DMC SPI Busy Bit:
0: Ready for next read or write access
1: Busy. The DMC SPI interface is still active 0 SPP: r