Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 429)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 429
8.4.2.11.4 Test Read Val Register
Address: 0xEC, TestReadValReg
Width: 32 bit
Register to read data for Hw test purposes
8.4.2.12 I2C interface to Dsps (I2CIfToDsp)
Resets:
Pwr = Power On Reset
1 TsipFullLoopbackToDsp RW 0b1:
TsipFullLoopbackToDspEnable
, All channels of the Tsip
Interface to the Dsps are
looped back immediately with
no bit and channel shift
0b0:
TsipFullLoopbackToDspDisabl
e, Tsip normal operation mode 0b0 X X
0 DspRxFrameSyncMode RW 0b1: SerDesLoopBack, Frame
sync of Dsp receiver is
adjusted to correspond with
different delay of serdes link in
loopback mode
0b0: SerDesNormal, Frame
sync of Dsp receiver is in
normal operation mode
0b0 X X
Table 8-225 Test Mode Control Register (continued)
Bit Acronym Type Description Default Pwr Soft
Table 8-226 Test Read Val Register
Bit Acronym Type Description Default Pwr Soft
31...0 TestReadData R Read data for Hw test purposes undef - -