Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 302)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 302
8.2.2.3.10 SPP BIOS IPMC Watchdog Timeout Register
When one of the IPMC Watchdog Timeout: bit of Table "IPMC Watchdog Timeout Register" on
page 305 is set the corresponding BIOS IPMC Watchdog Timeout bit is set. The BIOS clears this
status bit, writing one.
8.2.2.3.11 SPP OS Reset Source Indication Register
The Table 8-76 stores the source of the most recent reset. A one in the register bit indicates that
the associated reset has occurred. If more than one reset occurs from different sources without
clearing the corresponding register bits, one can not determine the most recent reset source
since more than one bit will be set. The same situation will happen, if two reset sources go
active at the same time.
OS should never write to this register.
Table 8-75 BIOS IPMC Watchdog Timeout Register
Address: 0x0D
Bit Description Default Access
0 SPP BIOS IPMC Watchdog Timeout:
1: IPMC Watchdog Timeout occurred PWR_GOOD:0 SPP: r/w1c
IPMC: r
1 SPP BIOS IPMC Pre-Timeout
1: IPMC Pre-Timeout occurred PWR_GOOD:0 SPP: r/w1c
IPMC: r
7:2 Reserved 0 r
BIOS should never write to this register.