Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 304)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 304
8.2.2.3.13 IPMC Reset Source Indication Register
The Table 8-78 stores the source of the most recent reset. A one in the register bit indicates that
the associated reset has occurred. If more than one reset occurs from different sources without
clearing the corresponding register bits, one can not determine the most recent reset source
since more than one bit will be set. The same situation will happen, if two reset sources go
active at the same time.
Table 8-77 OS IPMC Watchdog Timeout Register
Address: 0x0F
Bit Description Default Access
0 SPP BIOS IPMC Watchdog Timeout:
1: IPMC Watchdog Timeout occurred PWR_GOOD:0 SPP: r/w1c
IPMC: r
1 SPP BIOS IPMC Pre-Timeout
1: IPMC Pre-Timeout occurred PWR_GOOD:0 SPP: r/w1c
IPMC: r
7:2 Reserved 0 r
Table 8-78 IPMC Reset Source Indication Register
Address: 0x10
Bit Description Default Access
0 PWR_GOOD Payload Power-on reset
1: Reset occurred PWR_GOOD:1 IPMC: r/w1c
1 Reserved 0 r
2 PB_RST_ face plate push button reset
1: Reset occurred PWR_GOOD:0 IPMC: r/w1c
3 SW Programmable Hardware Watchdog reset
1: Reset occurred PWR_GOOD:0 IPMC: r/w1c
4 RTM_PB_RST_ Reset key at RTM
1: Reset occurred PWR_GOOD:0 IPMC: r/w1c
5 SPP_HRESET_REQ_ signal from SPP
1: Reset occurred PWR_GOOD:0 IPMC: r/w1c
6 Reserved 0 r