Cpld and fpga – Artesyn ATCA-8310 Installation and Use (May 2014) User Manual
Page 385
CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E)
385
Columns right of the default column contain a reset cause in the header row of the table and in
the table itself:.
- = bits are not affected by this reset
X = bits are set immediately to default value by this reset
F = bits are set to default value by connected function when this reset occurs
Reserved Bits within registers have an undefined value when read and should be written as read
before when written.
Reserved values:
* = all values of this bit/nibble position are reserved combinations
r = remaining not previously noted combinations of this bit/nibble positions are reserved
values
It is forbidden to write reserved combinations to registers.
[Hw: ...........] = Supplementary information about HW implementation, for HW review
purposes only
8.4.2.1
SerDes Client Interface (8bit each) (SerDesClientIf)
Resets:
Pwr = Power On Reset
Soft = Soft Reset
Provides register access to the SerDes client interface block as defined by Lattice. Higher
addresses are determined by SerDesPreselect Register. Control by SW or JTag via Orcastra is
determined.
8.4.2.1.1 SerDesPreselect Register
Address: 0x40, SerDesPselReg