Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 350)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 350
8.2.2.3.41 GPP Boot SPI Flash Access Registers
7 SPI Command
0: Write ARTM Register:
Triggers 16 SPI clocks and shifts the address and data out to MOSI.
1: Read ARTM Register:
Triggers 16 SPI clocks and shifts the address out to MOSI. The Data
on MISO is shifted in. 0 SPP: r/w
Table 8-167 ARTM SPI Access Data Register
Address: 0xD1
Bit Description Default Access
7:0 ARTM Write Data Register.
Write data before SPI Address and command written - SPP: w
ARTM Read Data Register.
Contains read data after SPI Address and command written 0 SPP: r
Table 8-166 ARTM SPI Access Control Register (continued)
Address: 0xD0
Bit Description Default Access
Table 8-168 GPP Boot SPI Flash Control Register
Address: 0xD2
Bit Description Default Access
0 GPP Boot SPI Flash Chip Select Control
1: Drive SPI Chip Select high
0: Drive SPI Chip Select low. 1 SPP: r/w
1 GPP Boot SPI Flash select
0: GPP Default Boot Flash
1: GPP Backup Boot Flash 0 SPP: r/w
5:2 Reserved 0 r