Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 307)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 307
There are several reset domains which may be separately asserted or deasserted by setting or
resetting the corresponding bit of the Reset Control Register.
Table 8-83 Reset Control Register
Address: 0x14 -0x15
Bit Description Default Access
0 GPP Reset PWR_GOOD: 1 SPP: r/w
IPMC: r/w
1 Broadcom Ethernet Switch Reset 0 SPP: r/w
2 DMC Base Reset 0 SPP: r/w
IPMC: r/w
3 DMC 1 Reset 0 SPP: r/w
IPMC: r/w
4 DMC 2 Reset 0 SPP: r/w
IPMC: r/w
5 ARTM Reset 0 SPP: r/w
IPMC: r/w
6 Telecom Clock Device ACS8520 Reset 0 SPP: r/w
IPMC: r/w
7 SRIO Reset 0 SPP: r/w
IPMC: r
15:8 Reserved 0 r