Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 402)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 402
This register indicates the number of the CRC errors since enabling the CRC error counting by
the ErrCntCtrlReg:CrcErrCntStart bit. The error counter sticks at 0xFFFFFF.
8.4.2.5.9 Disparity Error Count Register
Address: 0x94, DispErrCntReg
Width: 32 bit
This register indicates the number of the Disparity errors since enabling the Disparity error
counting by the ErrCntCtrlReg:DispErrCntStart bit. The error counter sticks at 0xFFFFFF.
8.4.2.6 DSP Reset and NMI Control Block (DspResNmiCtrlBlk)
Resets:
Pwr = Power On Reset
Soft = Soft Reset
This block controls the reset and NMI pins to ten TI Tomahawk DSPs (TMS320TCI6486).
Table 8-196 CRC Error Count Register
Bit Acronym Type Description Default Pwr Soft
31...24 - - reserved undef - -
23...0 CrcErrCnt R This register indicates the number of frames
with erroneous CRC. The error counter
sticks at 0xFFFFFF 0x0 F F
Table 8-197 Disparity Error Count Register
Bit Acronym Type Description Default Pwr Soft
31...24 - - reserved undef - -
23...0 DispErrCnt R This register indicates the number of
Disparity errors. The error counter sticks
at 0xFFFFFF 0x0 F F