Table 8-14, Power-up failure codes part 3 register, Table 8-15 – Artesyn ATCA-8310 Installation and Use (May 2014) User Manual
Page 253: Power-up failure codes part 4 register, Cpld and fpga
CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E)
253
Table 8-14 Power-up Failure Codes Part 3 Register
CPLD Address: 0x0A
Bit Description
Default
Access
0
1.8V Power Good GPP PLL failed. Last inverted Level
PWRGD_V1P8S_GPP
0
SPI: r
1
1.5V and 1.05V Power Good GPP failed. Last inverted Level
PWRGD_V1P5_GPP_V1P05
0
SPI: r
2
1.05V Power Good GPP VTT failed. Last inverted Level
PWRGD_V1P05S_VTT
0
SPI: r
3
1.0V Power Good SPP failed. Last inverted Level
PWRGD_V1P0_SPP
0
SPI: r
4
1.5V Power Good SPP failed. Last inverted Level
PWRGD_V1P5_SPP
0
SPI: r
5
GPP doesn't wake up. GPP SLP States are not all deasserted.
0
SPI: r
6
IMVP Core Power Good GPP failed. Last inverted Level
PWRGD_IMVP
0
SPI: r
7
GFX Core Power Good GPP failed. Last inverted Level
PWRGD_GFXVR
0
SPI: r
Table 8-15 Power-up Failure Codes Part 4 Register
CPLD Address: 0x0B
Bit Description
Default
Access
2:0
DMC Base, DMC 1 and DM 2 Power Good failed. Last inverted Level
PWRGD_DMC[2:0].
0
SPI: r
3
RTM Power Good failed. From Zone 3 P30. Last inverted Level
PWRGD_RTM.
0
SPI: r
4
RTM MGMT Power Good. Last Level PWRGD_MGMT_RTM_.
0
SPI: r
5
RTM Payload Power Good. Last Level PWRGD_PAYLOAD_RTM_.
0
SPI: r