Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 276)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 276
The state of the Divisor Latch Bit (DLAB), which is the MOST significant bit of the Serial Line
Control Register (SCR), affects the selection of certain of the UART registers. The DLAB bit must
be set high by the system software to access the Baud Rate Generator Divisor Latches (DLL and
DLM).
 GPP UART Registers DLAB=0
- Receiver Buffer Register (RBR)
Table 8-49 GPP UART Register Overview
LPC IO Address DLAB Bit value Description
Base 0 Receiver Buffer (RBR). Read Only
Base 0 Transmitter Holding (THR). Write Only.
Base + 1 0 Interrupt Enable Register (IER)
Base + 2 X Interrupt Identification Register (IIR). Read Only
Base + 2 X FIFO Control Register (FCR). Write Only.
Base + 3 X Line Control Register (LCR)
Base + 4 X Modem Control Register (MCR)
Base + 5 X Line Status Register (LSR). Read Only
Base + 6 X Modem Status Register (MSR). Read Only
Base + 7 X Scratch Pad Register (SCR).
Base 1 Divisor Latch LSB (DLL)
Base + 1 1 Divisor Latch MSB (DLM)