Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 289)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 289
- Scratch Register (SCR)
1 Change in data set ready (DDSR) indicator
DDSR indicates that the DSR# input has changed state since the
last time it was read by the CPU. When DDSR is set and the modem
status interrupt is enabled, a modem status interrupt is generated:
1: Change in state of DSR# input since last read
0: No change in state of DSR# input since last read 0 GPP: r/w
2 Trailing edge of the ring indicator (TERI) detector
TERI indicates that the RI# input to the chip has changed from a
low to a high level. When TERI is set and the modem status
interrupt is enabled, a modem status interrupt is generated. Not
supported. 0 GPP: r/w
3 Change in data carrier detect (DDCD) indicator
DDCD indicates that the DCD# input to the chip has changed state
since the last time it was read by the CPU. When DDCD is set and
the modem status interrupt is enabled, a modem status interrupt
is generated. Not supported. 0 GPP: r/w
4 Complement of the clear-to-send (CTS#) input
When the Asynchronous Communications Element (ACE) is in
diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the
MCR bit 1 (RTS#). Ext. GPP: r
5 Complement of the data set ready (DSR#) input
When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1),
this bit is equal to the MCR bit 0 (DTR#). Ext. GPP: r
6 Complement of the ring indicator (RI#) input
When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1),
this bit is equal to the MCR bit 2 (OUT1#). Not supported. Ext. GPP: r
7 Complement of the data carrier detect (DCD#) input
When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1),
this bit is equal to the MCR bit 3 (OUT2#). Not supported. Ext. GPP: r
Table 8-60 Modem Status Register (MSR) (continued)
IO Address: Base + 6
Bit
Description
Default Access