Table 8-69, Status register, Cpld and fpga – Artesyn ATCA-8310 Installation and Use (May 2014) User Manual
Page 297: 5 status register
CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E)
297
8.2.2.3.5 Status Register
6
Control green LED output Signal LED4_GR_:
0: LED4_GR_ is driven high.
1: LED4_GR_ is driven low.
0
SPP: r/w
GPP: r
IPMC: r
7
Control green LED output Signal LED4_RD_:
0: LED4_RD_ is driven high.
1: LED4_RD_ is driven low.
0
SPP: r/w
GPP: r
IPMC: r
Table 8-68 User LED Control Register (continued)
Address: 0x05
Bit Description
Default
Access
Table 8-69 Status Register
Address: 0x06 - 0x07
Bit Description
Default
Access
0
Level of Signal SPP_DMA1_DDONE0_
Ext.
r
1
Level of Signal SPP_DMA1_DACK0
Ext.
r
2
Level of Signal GPP_PM_SUS_STAT_
Ext.
r
3
Level of Signal GPP_SATA_LED_
Ext.
r
4
Level of Signal GPP_XDP_DBR_
Ext.
r
6:5
Reserved
0
r
7
Switch Register (bits 8 to 15) differ from default values:
0: No difference between SW_[7:0] and register bits 8 to 15
1: SW_[7:0] and register bits 8 to 15 differ at least at one bit
position
Write 1 to set register bits 8 to 15 back to default (inverted level of
Switch Signals SW_[7:0])
0
SPP:
r/w1c