Table 8-12, Power-up failure codes part 1 register, Table 8-13 – Artesyn ATCA-8310 Installation and Use (May 2014) User Manual
Page 252: Power-up failure codes part 2 register, Cpld and fpga, 5 power-up failure codes registers
CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E)
252
8.1.2.2.5 Power-up Failure Codes Registers
The cause of Power-up sequence failures or Power fails during payload running are accessible
by the IPMC via SPI Bus. The Power-Up Failure Codes Registers is latched status while failing.
When the IPMC repower the board, the registers are set to the default values.
Table 8-12 Power-up Failure Codes Part 1 Register
CPLD Address: 0x8
Bit
Description
Default
Access
3:0
Latched State when Power fail occurs.
0: No Error
Other: The number corresponds to the Power state machine encoding.
0
SPI: r
7:3
Reserved
0
r
Table 8-13 Power-up Failure Codes Part 2 Register
CPLD Address: 0x9
Bit
Description
Default
Access
0
12V Power Good failed. Last inverted Level PWRGD_VP12
0
SPI: r
1
5V Power Good failed. Last inverted Level PWRGD_VP5
0
SPI: r
2
3.3V Power Good failed. Last L inverted Level PWRGD_V3P3
0
SPI: r
3
2.5V Power Good failed. Last inverted Level PWRGD_V2P5
0
SPI: r
4
1.8V Power Good failed. Last inverted Level PWRGD_V1P8
0
SPI: r
5
1.2V Power Good failed. Last inverted Level PWRGD_V1P2
0
SPI: r
6
1.2V Power Good Ethernet failed. Last inverted Level PWRGD_V1P2
Ethernet
0
SPI: r
7
1.0V Power Good failed. Last inverted Level PWRGD_V1P0
0
SPI: r