Table 8-186, Serdes transmitter status register, Table 8-187 – Artesyn ATCA-8310 Installation and Use (May 2014) User Manual
Page 395: Supplemental test pattern transmit register, Cpld and fpga, 2 serdes transmitter status register, 3 supplemental test pattern transmit register
CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E)
395
8.4.2.4.2 Serdes Transmitter Status Register
Address: 0x71, SerDesTrmStatReg
Width: 8 bit
The Serdes transmitter status is shown
8.4.2.4.3 Supplemental Test Pattern Transmit Register
Address: 0x72, SupplTstPatTrmReg
Width: 16 bit
Static Test Pattern from the Tsip2SerTstPatReg are transmitted via the supplementary channel
towards the serial interface.
Table 8-186 Serdes Transmitter Status Register
Bit
Acronym
Type
Description
Default
Pwr
Soft
7
SerdesTrmPllLolFlag
R
0b1: SerdesTrmPllLolFlag, Set
when the Serdes transmitter PLL
has lost lock. Reset by respective
bit in SerDesTrmCtrlReg
0b0
F
F
6...4
-
-
reserved
undef
-
-
3
SerdesTrmPllLol
R
0b1: SerdesTrmPllLol, Shows
actual status of Serdes
transmitter PLL lock.
0b0
F
F
2...0
-
-
reserved
undef
-
-
Table 8-187 Supplemental Test Pattern Transmit Register
Bit
Acronym
Type
Description
Default
Pwr
Soft
15...0
SupplTstPatTrmData
RW
Test pattern for
transmission via the
supplementary channel
towards the serial
interface
0x0
X
X