Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 411)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 411
8.4.2.7.6 DSP Host Event Interrupt Status Reset Register
Address: 0xAA, DspHevStaResReg
Width: 16 bit
9 DspWdgRes9 RW 0b1: DspWdgRes9, resets DspWdg9
bit in DspHevWdgStaReg 0b0 X X
8 DspWdgRes8 RW 0b1: DspWdgRes8, resets DspWdg8
bit in DspHevWdgStaReg 0b0 X X
7 DspWdgRes7 RW 0b1: DspWdgRes7, resets DspWdg7
bit in DspHevWdgStaReg 0b0 X X
6 DspWdgRes6 RW 0b1: DspWdgRes6, resets DspWdg6
bit in DspHevWdgStaReg 0b0 X X
5 DspWdgRes5 RW 0b1: DspWdgRes5, resets DspWdg5
bit in DspHevWdgStaReg 0b0 X X
4 DspWdgRes4 RW 0b1: DspWdgRes4, resets DspWdg4
bit in DspHevWdgStaReg 0b0 X X
3 DspWdgRes3 RW 0b1: DspWdgRes3, resets DspWdg3
bit in DspHevWdgStaReg 0b0 X X
2 DspWdgRes2 RW 0b1: DspWdgRes2, resets DspWdg2
bit in DspHevWdgStaReg 0b0 X X
1 DspWdgRes1 RW 0b1: DspWdgRes1, resets DspWdg1
bit in DspHevWdgStaReg 0b0 X X
0 DspWdgRes0 RW 0b1: DspWdgRes0, resets DspWdg0
bit in DspHevWdgStaReg 0b0 X X
Table 8-204 DSP Watchdog Interrupt Status Reset Register (continued)
Bit Acronym Type Description Default Pwr Soft