Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 340)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 340
 Failover Interrupt Registers
Table 8-149 Failover Interrupt Registers
Address: 0xA4 - 0xA5
Bit Interrupt Name Description Default Access
0 ROLE_CHANGE Role Change 0 SPP: r/w1c
1 HEALTHY_O_D Local Healthy deasserted 0 SPP: r/w1c
2 HEALTHY_I_D Remote Healthy deasserted 0 SPP: r/w1c
3 HEALTHY_I_A Remote Healthy asserted 0 SPP: r/w1c
4 SPP_RESET SPP Reset. Local Healthy deasserted.
Note: May not be masked. PWR_G
OOD: 0 SPP: r/w1c
15:5 - Reserved 0 r
Table 8-150 SPP Failover Interrupt Enable Register
Address: 0xA6 - 0xA7
Bit Interrupt Name Description Default Access
0 ROLE_CHANGE Role Change enable:
0: Disabled
1:Enabled 0 SPP: r/w
1 HEALTHY_O_D Local Healthy deasserted enable:
0: Disabled
1:Enabled 0 SPP: r/w
2 HEALTHY_I_D Remote Healthy deasserted enable:
0: Disabled
1:Enabled 0 SPP: r/w
3 HEALTHY_I_A Remote Healthy asserted enable:
0: Disabled
1:Enabled 0 SPP: r/w