Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 362)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 362
8.2.3.11.6 GPP Boot Status Register
Register is set by BIOS / OS to indicate boot progress.
Register can be read by SPP and IPMC.
8.2.3.11.7 RTC Counter
There is 32 bit counter in the Glue Logic FPGA, which is incremented each second. Counter
starts after power good. SPP can write start value. SPP, GPP and IPMC may read counter value.
A read or write access of the most significant byte (bits 24 to 31) of the register latches the read
value or take over the 32 bit start value in case of a write.
8.2.3.12 SPP Failure Detection
The Figure 8-9 shows Failover schema for inactive ADM Mode.
The ADM Mode is not jet described Add HELATH_I enable gate!