Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 300)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 300
7 SPI Command
0: Write CPLD Register:
Triggers 16 SPI clocks and shifts the address and data out to MOSI.
1: Read CPLD Register:
Triggers 16 SPI clocks and shifts the address out to MOSI. The Data
on MISO is shifted in. 0 SPP: r/w
GPP: r/w
Table 8-73 CPLD SPI Access Data Register
Address: 0x0B
Bit Description Default Access
7:0 CPLD Write Data Register.
Write data before SPI Address and command written - SPP: w
GPP: w
CPLD Read Data Register.
Contains read data after SPI Address and command written 0 SPP: r
GPP: r
Table 8-72 CPLD SPI Access Control Register (continued)
Address: 0x0A
Bit Description Default Access
SPP or GPP should read or write to the Table "CPLD SPI Access Data Register" on page 300
only when Busy Bit in Table "CPLD SPI Access Control Register" on page 299 .