Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 322)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 322
The following tables refer to the clock selected with Table "Telecom Clock Monitor Select
Register" on page 322 .
15:8 Reserved 0 r
Table 8-116 Telecom Clock Monitor Select Register
Address: 0x68
Bit Description Default Access
3:0 Select supervised Telecom Clocks 0 to 15
0-7: Select corresponding clock.
8:15: Reserved 0 SPP: r/w
6:4 Reserved 0 r
7 Locked. 0 SPP: r/w
Table 8-117 Telecom Clock Monitor Time Base Register
Address: 0x69
Bit Description Default Access
1:0 Select Time base for clock supervision:
0: Time Base is 0.5ms
1: Time Base is 64ms
2: Time Base is 1024ms
3: Time Base is 32.768s 0 SPP: r/w
7:2 Reserved 0 r
Table 8-115 Telecom Clock Monitor Out of Range Register (continued)
Address: 0x66 - 0x67
Bit Description Default Access