Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 437)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 437
The meaning of the LEDs is defined as follows:
Table 8-229 DSP FPGA debug LEDs
Power / Reset indication
DebugLed[7] DebugLed[6]
On Off device loaded
On ON:Off 1:3 LED 6 blip wait for
dmc_pwren activation
On ON:Off 1:1 LED 6 blink wait for power
good
ON:Off 1:1 On LED 6 on / LED 7 blink for
normal operation
Serdes link to RTM FPGA indication
DebugLed[5] On - Serdes Transmit PLL
locked Off - loss of lock
DebugLed[4] On - Serdes Receive PLL
locked Off - loss of lock
DebugLed[3] On - Serdes Receiver has
found comma
SW interface
DebugLed[2] DebugLedReg Bit 2
DebugLed[1] DebugLedReg Bit 1
DebugLed[0] DebugLedReg Bit 0