Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 407)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 407
This Block is connected to the status lines (DSP_RESETSTAT_N, DSP_BOOTACTIVE) and
interrupt lines (DSP_HOUT, DSP_WDOUT) of each DSP. The status of all lines can be read from
the Status and Interrupt Monitor Registers. DSP interrupts (DSP_HOUT, DSP_WDOUT) are
forwarded to the controller cpu.
8.4.2.7.1 DSP Boot Status Register
Address: 0xA0, DspBootStaReg
Width: 16 bit
This register monitors the Boot status of 10 DSPs.
8.4.2.7.2 DSP Reset Status Register
Address: 0xA2, DspResStaReg
Width: 16 bit
Table 8-200 DSP Boot Status Register
Bit Acronym Type Description Default Pwr Soft
15...10 - - reserved undef - -
9 DspBoot9 R 0b1: DspBoot9, active if DSP9 boot is active 0b0 F F
8 DspBoot8 R 0b1: DspBoot8, active if DSP8 boot is active 0b0 F F
7 DspBoot7 R 0b1: DspBoot7, active if DSP7 boot is active 0b0 F F
6 DspBoot6 R 0b1: DspBoot6, active if DSP6 boot is active 0b0 F F
5 DspBoot5 R 0b1: DspBoot5, active if DSP5 boot is active 0b0 F F
4 DspBoot4 R 0b1: DspBoot4, active if DSP4 boot is active 0b0 F F
3 DspBoot3 R 0b1: DspBoot3, active if DSP3 boot is active 0b0 F F
2 DspBoot2 R 0b1: DspBoot2, active if DSP2 boot is active 0b0 F F
1 DspBoot1 R 0b1: DspBoot1, active if DSP1 boot is active 0b0 F F
0 DspBoot0 R 0b1: DspBoot0, active if DSP0 boot is active 0b0 F F